1. Field of the Invention
The present invention relates to a thin film transistor ("TFT") being a semiconductor device, and more particularly to a thin film transistor and fabricating method therefor for vertically forming a drain region, a gate electrode and a source region to reduce an area occupied by a cell, and encircling a channel region by the gate electrode to improve a transistor characteristic, thereby being suitable for a SRAM cell of high packing density.
2. Description of the Prior Art
Generally, a thin film transistor is widely utilized in place of a road resistor in SRAM cells of 1M and higher, or as a switching device for switching a picture data signal of respective pixel areas in liquid crystal displays.
The thin film transistor widely available in various fields preferably has small off current and large on current. For example, in adapting it to the SRAM cells, the power dissipated can be economized and a memory characteristic of a cell can be enhanced.
FIG. 1 is a sectional view illustrating a structure of a conventional P-type MOS thin film transistor fabricated to improve the on/off current ratio.
The conventional P-type MOS thin film transistor has a predetermined gate electrode 12 formed by depositing polysilicon on a P-type silicon substrate 11. A gate insulating layer 13 is formed on the gate electrode 12. A source region 14a and a drain region 14b are formed on the gate insulating layer 13 by the deposition of a body polysilicon 14 and ion implantation of a P-type impurity BF.sub.2.
FIGS. 2A to 2D are views for illustrating a process for fabricating the conventional P-type MOS thin film transistor.
Referring to FIG. 2A, the polysilicon is deposited on the substrate 11 or an insulating layer (not shown). Successively, the polysilicon is patterned via a photolithography by means of a gate mask to form the gate electrode 12.
As shown in FIG. 2B, the gate insulating layer 13 and body polysilicon 14 are sequentially deposited on the substrate 11 which includes the gate electrode 12 thereon via a chemical vapor deposition (CVD). Then, the grain size of the body polysilicon is grown via a thermal diffusion method that performs a thermal treatment around a temperature of 600.degree. C. for 24 hours or so.
In FIG. 2C, a photoresist layer 15 is deposited on the body polysilicon 14 to be exposed and developed for masking the source region and drain region. At this time, the masking process is performed to force the source region to overlap the gate electrode 12, and drain region to offset to the gate electrode 12.
The P-type impurity BF.sub.2 is ion-implanted onto the body polysilicon 14 of which channel region is masked as described above to form the source region 14a and drain region 14b, thereby completing the conventional P-type MOS thin film transistor.
In a conventional P-MOS thin film transistor, the separation between the source and drain structure, which defines the channel, was oriented in a direction substantially parallel to the substrate thereby causing the TFT to occupy a large cell area, so that it is not well suited for manufacturing SRAM cells of high packing density.
Also, since the gate electrode formed on the substrate controls the electric charge within the channel, a second gate insulating layer is deposited on the body polysilicon and a second gate is formed thereon in order to inverse overall channel, thereby resulting in a problem of increasing steps in the cell.
Moreover, a mask must be used whenever the gate electrode and channel region are formed, so that the processing for manufacturing thereof is increased to raise manufacturing cost.